This invention relates to digital-to-analog (D/A) converters such as are used in pulse code modulation systems of communication.
The function of the ideal D/A converter is to operate on a digital number and convert it to a voltage or current proportional to the number. In communication systems the digital numbers represent points taken at regular sampling intervals from a continuous waveform. The ideal converter should in this case produce a continuous analog output which is the result of drawing a smooth curve through the sample points and which contains no component above half sampling frequency. In practice this is usually achieved using a precision switched resistor ladder network which holds each sample constant for one sample period and then suppressing unwanted components in the output spectrum by means of a low pass filter. Ladder networks are expensive and cannot easily be integrated with the degree of precision required in communication systems.
An alternative that is more amenable to digital integration uses a rate multiplier. This is a simple logical device producing an output pulse stream whose mean density is proportional to a clock frequency times the input number. Since the input number is changed at each sample instant the clock frequency must be equal to the sampling frequency times the number of possible levels in the input number. For example a 12 bit linear PCM at 8kHz (kilohertz) sampling rate would require a clock frequency of 32.768MHz (megahertz). A compromise converts the PCM words to sign, magnitude and scaling components. The magnitude is applied to a rate multiplier running at a more modest clock frequency the output of which is scaled and signed by analog means.